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Freescale Semiconductor /MK21D5WS /SPI1 /CTAR_SLAVE

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Interpret as CTAR_SLAVE

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0RESERVED0RESERVED 0RESERVED 0 (0)CPHA 0 (0)CPOL 0FMSZ

CPHA=0, CPOL=0

Description

Clock and Transfer Attributes Register (In Slave Mode)

Fields

RESERVED

no description available
RESERVED

no description available
RESERVED

no description available
CPHA

Clock Phase

0 (0): Data is captured on the leading edge of SCK and changed on the following edge.

1 (1): Data is changed on the leading edge of SCK and captured on the following edge.
CPOL

Clock Polarity

0 (0): The inactive state value of SCK is low.

1 (1): The inactive state value of SCK is high.
FMSZ

Frame Size

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data